DocumentCode :
1639696
Title :
A 14-bit 100 MS/s self-calibrated DAC with a randomized calibration-period
Author :
Qiu, Dong ; Fang, Sheng ; Xie, Renzhong ; Li, Ran ; Yi, Ting ; Hong, Zhiliang
Author_Institution :
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
fYear :
2010
Firstpage :
312
Lastpage :
314
Abstract :
A 14-bit 100MS/s self-calibrated Digital-to-Analog converter (DAC) is presented. Analog background self-calibration technique with a randomized calibration-period is adopted to improve the dynamic performance. The DAC is fabricated in SMIC 0.13-μm CMOS process and occupies a 1.29mm2 die area. The measured DNL/INL is better than 3.1LSB/4.3LSB. The SFDR is 72.8dB at 1MHz signal and 100MHz sampling frequency. And the current consumption is 50mA under 1.2/3.3V dual power supplies for digital and analog part, respectively.
Keywords :
CMOS integrated circuits; digital-analogue conversion; power supply circuits; CMOS process; analog background self-calibration; current 50 mA; digital-to-analog converter; dual power supplies; randomized calibration-period; self-calibrated DAC; size 0.13 mum; voltage 1.2 V; voltage 3.3 V; word length 14 bit; Arrays; Calibration; Clocks; Current measurement; Generators; Power supplies; Semiconductor device measurement;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-5797-7
Type :
conf
DOI :
10.1109/ICSICT.2010.5667743
Filename :
5667743
Link To Document :
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