Digitally-assisted sample-to-sample jitter correction in ADC systems

In this paper we present a technique that permits the correction of errors caused by the timing jitter associated with sampling clocks cadencing analog-to-digital converters (ADCs). The correction system is digital, completely independent of the front-end ADC and corrects the data out of the converter on a sample-to-sample basis. Relative to the ADC under consideration, the proposed technique enables quasi-zero jitter sampling characteristics which is demonstrated experimentally in this paper.