A 120 MHz SC 4th-order elliptic interpolation filter with accurate gain and offset compensation for direct digital frequency synthesizer

Author

U, Seng-Pan ; Neves, R. ; Martins, R.P. ; Franca, J.E.

Author_Institution

Fac. of Sci. & Technol., Macau Univ., Macau

fYear

1999

fDate

6/21/1905 12:00:00 AM

Firstpage

1

Lastpage

4

Abstract

This paper proposes an optimum design of a high frequency Switched-Capacitor IIR interpolation filter for Direct Digital Frequency Synthesizer systems. The circuit is formed by the combination of novel double sampling recursive direct-form II and non-recursive polyphase structures embedding mismatch-free analog delay lines with accurate, wideband gain- and offset-compensation achieved by Predictive Correlated-Double Sampling techniques. This filter is designed with optimized speed of the analog components in AMS 0.35 μm CMOS technology, occupies about 0.4 mm² active area and consumes about 22 mW at 3.0 V supply

Keywords

CMOS analogue integrated circuits; IIR filters; compensation; direct digital synthesis; elliptic filters; interpolation; switched capacitor filters; 0.35 micron; 120 MHz; 22 mW; 3.0 V; AMS CMOS technology; analog delay line; design optimization; direct digital frequency synthesizer; gain compensation; high frequency circuit; offset compensation; polyphase structure; predictive correlated double sampling; switched capacitor IIR elliptic interpolation filter; CMOS technology; Circuits; Delay lines; Design optimization; Digital filters; Frequency synthesizers; IIR filters; Interpolation; Sampling methods; Wideband;

fLanguage

English

Publisher

ieee

Conference_Titel

ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-5705-1

Type

conf

DOI

10.1109/APASIC.1999.824010

Filename

824010