Performance and power analysis of long line interconnection torus networks for Network-on-Chips

With increasing scale of Network-on-Chips (NoCs), the power caused by long line wires between cores counts for a significant proportion of the NoCs energy consumption. Most of the study on NoCs topologies assume that interconnect wires between cores are same length and are short lines. Taking 2D 4×4 torus network as an example in this paper, we present a long line interconnects network model for analyzing latency and energy consumption of NoCs. Simulation shows the different between this model and short line model. We also propose a novel approach based on low swing circuit using MOS current mode logic (MCML) to decreasing power consumption of long line wires in NoCs. Compared to the conventional full swing circuit, Simulation results show that the total NoCs link energy consumption can be reduced.