Title :
Design and implementation for 125 mW/MIPS ultra-high speed low power asymmetric digital subscriber line transceiver chip
Author :
Na, Seong-Jo ; Lee, Seung-Min ; Chung, Jin-Hong ; Seung-Min Lee ; Kim, J.H.
Author_Institution :
Dept. of Inf. & Commun. Eng., Dongshin Univ., Chonnam, South Korea
fDate :
6/21/1905 12:00:00 AM
Abstract :
Multimedia service with audio and video have become most desirable as the ADSL technology ideally converted from 1.5 Mbps full duplex HDSL technology via two twist-pair into 6.144 Mbps transmission technology via single twist-pair. This results in an interactive transmission service of T1 & E1 class data using the subscriber line without repeaters. The ADSL transceiver chipset is configured by DMT (Discrete Multi Tone modulation) scheme and RISC-based DSP core structure. Our ADSL chip is to be used in VOD, interactive interact service and/or teleconferencing system, etc. The operating frequency and dissipated power of the chip are 40 MHz and 5 W at 5 V
Keywords :
application specific integrated circuits; digital signal processing chips; digital subscriber lines; low-power electronics; multimedia communication; reduced instruction set computing; telecommunication computing; teleconferencing; transceivers; trellis coded modulation; very high speed integrated circuits; video on demand; 125 MIPS; 125 mW to 5 W; 40 MHz; 5 V; 6.144 Mbit/s; ADSL transceiver chip; ASIC; DMT; E1 class data; RISC-based DSP core structure; T1 class data; VOD; asymmetric digital subscriber line; discrete multitone modulation; interactive interact service; low power operation; teleconferencing system; ultra-high speed operation; Decoding; Digital signal processing chips; Frequency; Interference; Multimedia systems; OFDM modulation; Repeaters; Teleconferencing; Telephony; Transceivers;
Conference_Titel :
ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on
Conference_Location :
Seoul
Print_ISBN :
0-7803-5705-1
DOI :
10.1109/APASIC.1999.824014
