Title :
Design and simulation of three ATM ASICs
Author :
Kim, Chan ; Jun, Jong Arm ; Lee, Sang Ho ; Kim, Jae Geun
Author_Institution :
Switching & Transmission Labs., ETRI, Taejon, South Korea
fDate :
6/21/1905 12:00:00 AM
Abstract :
In ASIC development, effective simulation leads into functionally more reliable chips as well as faster development time. This paper describes the design and the simulation techniques used in 3 ATM ASIC developments in ETRI. The three ASICs described are: ASAH-NIC-a 155 Mbps ATM SAR chip with internal PCI interface and SDH framer; ASAPI-L4-a 622 Mbps bidirectional ATM layer processing chip with UPC, OAM, QOS buffering capabilities; and ASAH-P4-a 622 Mbps ATM physical layer chip
Keywords :
application specific integrated circuits; asynchronous transfer mode; circuit CAD; circuit simulation; digital signal processing chips; telecommunication computing; telecommunication equipment; 155 Mbit/s; 622 Mbit/s; ASAH-NIC; ASAH-P4; ASAPI-L4; ATM ASICs; ATM SAR chip; ATM physical layer chip; ETRI; OAM buffering capability; QOS buffering capability; SDH framer; UPC buffering capability; bidirectional ATM layer processing chip; internal PCI interface; simulation techniques; Application specific integrated circuits; Assembly; Asynchronous transfer mode; Decoding; Master-slave; Physical layer; Random access memory; Synchronous digital hierarchy; Testing; Virtual colonoscopy;
Conference_Titel :
ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on
Conference_Location :
Seoul
Print_ISBN :
0-7803-5705-1
DOI :
10.1109/APASIC.1999.824019
