Title :
A fully programmable frame synchronization architecture of OFDM systems implemented on a multi-core processor platform
Author :
Fan, Wenhua ; Huang, Bei ; Cao, Jialin ; Chen, Yun ; Yu, Zhiyi ; Zeng, Xiaoyang
Author_Institution :
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
Abstract :
This paper presents a fully programmable frame synchronization architecture of OFDM systems implemented on a multi-core processor platform. By utilizing the guard interval in OFDM signals, the coarse symbol synchronization (CSS) and the fractional carrier frequency offset estimation (CFO) are considered simultaneously. The multi-core processor platform is a 2-Dimension mesh array of SIMD (Single Instruction Multiple Data) cores, and is well suited for digital communication applications. By exploring the task-level parallelism on many cores, data-level parallelism on SIMD cores, minimization of memory access, and route-length-minimized task mapping techniques, the implementation can achieve a throughput up to 224Mbps, which shows the great advantage of multi-core processor platform.
Keywords :
OFDM modulation; digital communication; microprocessor chips; multiplexing equipment; parallel processing; 2D mesh array; OFDM system; SIMD; coarse symbol synchronization; digital communication application; fractional carrier frequency offset estimation; multicore processor platform; programmable frame synchronization; single instruction multiple data cores; task level parallelism; Frequency estimation; Multicore processing; OFDM; Program processors; Synchronization; Throughput;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-5797-7
DOI :
10.1109/ICSICT.2010.5667757
