Architectural design and implementation of full ATM layer functions for the cost effective access network

As the various types of application services are increased in the ATM (asynchronous transfer mode) network, it becomes a very important requirement for ATM network equipment to provide for higher transfer rate and to detect the network failure or the service degradation. In order to meet these requirements we developed a monolithic single chip device which can handle VPI/VCI address translation, routing, UPC (usage parameter control), QOS (quality of service) buffering, ABR (available bit rate) processing and OAM (operation and management) processing for 65,536 VCs (virtual circuits) in real time. This paper describes architectural design and implementation of a 622 Mbps ATM layer ASIC (application specific integrated circuit). This ASIC is applicable to develop the network equipment in B-ISDN. This supports both NNI (network-network interface) and UNI (user-network interface)