A digital signal processor for low power

Author

Jang, Ho Rang ; Kim, Seung Hyun ; Chang, Young Hoon

Author_Institution

CE Lab., Samsung Adv. Inst. of Technol., YongIn, South Korea

fYear

1999

fDate

6/21/1905 12:00:00 AM

Firstpage

42

Lastpage

45

Abstract

Low power in digital signal processor design has been a critical design constraint since portable battery operated devices prevailed. Most of the power dissipation of a processor is in the clock network and the on-chip memory. By optimizing the critical path of the processor we could reduce the power of clock network. We propose an energy-efficient instruction set architecture to reduce the power consumption of the program memory access. We applied it to a digital hearing aid, and reduced the program memory size by approximately 75%

Keywords

clocks; digital signal processing chips; hearing aids; instruction sets; integrated circuit design; low-power electronics; DSP design; clock network; critical path; design constraint; digital hearing aid; digital signal processor; energy-efficient instruction set architecture; on-chip memory; portable battery operated devices; power consumption; program memory access; Auditory system; Batteries; Clocks; Digital signal processors; Energy consumption; Energy efficiency; Network-on-a-chip; Power dissipation; Process design; Signal design;

fLanguage

English

Publisher

ieee

Conference_Titel

ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-5705-1

Type

conf

DOI

10.1109/APASIC.1999.824025

Filename

824025