A quad multi-speed serializer/deserializer with analog adaptive equalization

Author

Wang, Hui ; Jiang, Xicheng ; Tam, Derek ; Cheung, Felix ; Cheung, Darwin ; Tong, Wynstan ; Le, Michael ; Wakayama, M. ; Van Engelen, Jurgen ; Parthasarathy, Vasudevan ; Baumer, Howard ; Buchwald, Aaron

Author_Institution

Broadcom Corp., Irvine, CA, USA

fYear

2004

Firstpage

340

Lastpage

343

Abstract

A quad multi-speed (1.25/1.5625/2.5/3.125Gb/s) serializer/deserializer implemented in 0.25μm CMOS technology is described. It uses a 4× interleaved sample-and-hold receiver architecture. An analog adaptive receiver equalizer and a linear phase detector are used for clock and data recovery. At 3.125Gb/s, the serializer RMS jitter is 2.4ps. The serializer/deserializer runs error free for 2³¹-1 PRBS data pattern over various length, up to 40-inches, of FR4 PCB trace.

Keywords

CMOS integrated circuits; adaptive equalisers; synchronisation; 0.25 micron; 0.25μm CMOS technology; 3.125 Gbit/s; PRBS data pattern; analog adaptive equalization; clock and data recovery; interleaved sample-and-hold receiver architecture; linear phase detector; quad multi-speed serializer/deserializer; Adaptive equalizers; Backplanes; Bandwidth; CMOS technology; Clocks; Decision feedback equalizers; Finite impulse response filter; Phase locked loops; Timing; Transmitters;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on

Print_ISBN

0-7803-8287-0

Type

conf

DOI

10.1109/VLSIC.2004.1346609

Filename

1346609