A multithreaded processor core with low overhead context switch for IP-packet processing

In this paper a multithreaded processor with hardware context switch mechanism driven by external events is presented for multi-processor system on chip (MPSoC). Combining this mechanism with asynchronous memory access the proposed processor implements Non-preemptive thread scheduling which can assure fairness of threads and optimization for single thread. The overhead of hardware thread switch is reduced to 0-1 clock cycle with this structure. Proposed multithreaded processor is designed based on 5 stages pipeline RISC processor in order for easier realization. FPGA simulation results show that the whole performance of the proposed structure improves about 3.8 times than the baseline one with area increased only 7%. It shows perfect performance/area ratio.