Performance optimization of n-MOSFETs using asymmetric interfacial oxide layer

A structure with an asymmetric interfacial oxide layer is proposed to improve device performance in n-channel MOSFETs. The performance loss from mobility degradation, which results from thin interfacial oxide layers, can be mitigated by using a relatively thick interfacial oxide layer near source regions, while maintaining reasonable short channel effects through a relatively thin interfacial oxide layer near drain regions. TCAD simulation shows sizable device performance gain in the structure with an asymmetric interfacial oxide layer as compared with structures with symmetric interfacial oxide layers.