An inner product processor design using novel parallel counter circuits

This paper presents a novel parallel inner product processor architecture. The proposed processor has the following features: (1) it can be easily reconfigured for computing inner products of input arrays with four or more types of structures. Typically, each input array may contain 64 8-bit items, or 16 16-bit items, or 4 32-bit items, or 1 64-bit item, with items in unsigned or 2´s complement form; (2) it can be pipelined to produce inner products efficiently,; (3) it has a compact VLSI area with very simple reconfigurable components. The processor mainly consists of an array of 8×8 or 4×4 small multipliers plus two or three arrays of adders. The total amount of hardware is comparable to a single 64×64 array multiplier; (4) The whole network is reconfigured through using a few control bits for the desired computations, and the reconfiguration can be done dynamically; (5) The design is highly regular and modular, and most parts of the network are symmetric and repeatable. (6) A set of high performance parallel counter circuits are utilized in the design