DocumentCode
1640528
Title
A 90nm 6.5GHz 128×64b 4-read 4-write ported parameter variation tolerant register file
Author
Agarwal, Arnit ; Roy, Kaushik ; Hsu, Steven ; Krishnamurthy, Ram K. ; Borkar, Shekhar
Author_Institution
Dept. of ECE, Purdue Univ., West Lafayette, IN, USA
fYear
2004
Firstpage
386
Lastpage
387
Abstract
This paper describes a 128×64b 4-read, 4-write ported register file for 6.5GHz operation in 1.2V 90nm CMOS technology. A wordline underdrive technique combined with local bitline merge NAND whose P/N skew is optimally programmable based on die leakage enables 12% faster performance with 20% reduction in delay variation and 5× reduction in robustness failing dies over optimized high-performance conventional implementation.
Keywords
CMOS logic circuits; CMOS memory circuits; 1.2 V; 4-read 4-write ported parameter variation tolerant register file; 6.5 GHz; 90 nm; 90nm CMOS technology; P/N skew; die leakage; local bitline merge NAND; wordline underdrive technique; CMOS technology; Circuit noise; Clocks; Degradation; Delay; Noise robustness; Performance loss; Power generation; Registers; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on
Print_ISBN
0-7803-8287-0
Type
conf
DOI
10.1109/VLSIC.2004.1346624
Filename
1346624
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