Title :
A novel multi-core processor for communication applications
Author :
Xiao, Ruijin ; Quan, Heng ; You, Kaidi ; Huang, Bei ; Zeng, Xiaoyang ; Yu, Zhiyi
Author_Institution :
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
Abstract :
This paper proposes a novel multi-core processor with SIMD(Single Instruction Multiple Data) ISA (Instruction Set Architecture) and extended register file for communication applications. To acquire better parallel computing capability, we implement SIMD ISA and increase the number of register file from 32 to 64. 5×5 homogeneous 2-D mesh NoC (Network-on-Chip) topology is adopted to further enhance the parallelism, scalability and programmability. RS (Reed-Solomon) (255,239,8) decoding algorithm is implemented to evaluate the performance. Simulation result shows it could achieve 2.175 Gbps of throughput in worst case of RS 8-error incoming codeword under a maximum 350MHz clock frequency at SMIC 0.13um worst process corner, and the throughput is higher than other published implementations.
Keywords :
Reed-Solomon codes; computer architecture; multiprocessing systems; network topology; network-on-chip; parallel processing; 2D mesh NoC topology; ISA; Reed-Solomon decoding; SIMD; communication applications; extended register file; instruction set architecture; multi-core processor; network-on-chip; single instruction multiple data; Clocks; Decoding; Multicore processing; Parallel processing; Program processors; Registers; Throughput;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-5797-7
DOI :
10.1109/ICSICT.2010.5667778
