IP design of a reconfigurable baseline JPEG coding

Author

Chang, Hao-Chieh ; Chen, Li-Lin ; Lian, Chung-Jr ; Chang, Yung-Chi ; Chen, Liang-Gee

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

1999

fDate

6/21/1905 12:00:00 AM

Firstpage

143

Lastpage

146

Abstract

IP design of a complete, reconfigurable baseline JPEG encoder is presented in this paper. It features completely JFIF (JPEG File Interchange Format) compatible bit-stream output and a user-defined quantization table that can be re-configured at the run time and the compiling time. Thus, various hardware configurations can be easily achieved. Besides, modularized design is practiced such that smooth data flow in this pipelined architecture can be easily achieved by utilizing a central controller. This technique improves system performance greatly

Keywords

CMOS digital integrated circuits; application specific integrated circuits; code standards; data compression; digital signal processing chips; image coding; pipeline processing; reconfigurable architectures; 0.6 micron; CMOS ASIC; DSP chip; IP design; JFIF compatible bit-stream output; JPEG File Interchange Format; central controller; core pipelined architecture; image compression; image encoding hardware architecture; modularized design; reconfigurable baseline JPEG coding; user-defined quantization table; Application software; Bandwidth; Digital cameras; Discrete cosine transforms; Hardware; Image coding; Image quality; Image resolution; Quantization; Transform coding;

fLanguage

English

Publisher

ieee

Conference_Titel

ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-5705-1

Type

conf

DOI

10.1109/APASIC.1999.824048

Filename

824048