• DocumentCode
    1640761
  • Title

    CMOS transceiver with baud rate clock recovery for optical interconnects

  • Author

    Emami-Neyestanak, Azita ; Palermo, Samuel ; Lee, Hae-Chang ; Horowitz, Mark

  • Author_Institution
    Comput. Syst. Lab., Stanford Univ., CA, USA
  • fYear
    2004
  • Firstpage
    410
  • Lastpage
    413
  • Abstract
    An efficient baud rate clock and data recovery architecture is applied to a double sampling/integrating front-end receiver for optical interconnects. Receiver performance is analyzed and projected for future technologies. This front-end allows use of a 1:5 demux architecture to achieve 5Gb/s in a 0.25 μm CMOS process. A 5:1 multiplexing transmitter is used to drive VCSELs for optical transmission. The transceiver chip consumes 145mW per link at 5Gb/s with a 2.5V supply.
  • Keywords
    CMOS integrated circuits; optical interconnections; surface emitting lasers; synchronisation; transceivers; 0.25 micron; 145 mW; 5 Gbit/s; CMOS transceiver; baud rate clock recovery; demux architecture; double sampling/integrating front-end receiver; optical interconnects; optical transmission; transceiver chip; CMOS process; CMOS technology; Clocks; Optical interconnections; Optical receivers; Optical transmitters; Performance analysis; Sampling methods; Transceivers; Vertical cavity surface emitting lasers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on
  • Print_ISBN
    0-7803-8287-0
  • Type

    conf

  • DOI
    10.1109/VLSIC.2004.1346633
  • Filename
    1346633
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1640761