DocumentCode :
1640792
Title :
Magnitude detection and phase synchronization of unbalanced and distorted grid voltage with novel extended PLL loop filter
Author :
Mian Wang ; Dongchang Qu ; Zhaohui Sun ; Guozhu Chen
Author_Institution :
Coll. of Electr. Eng., Zhejiang Univ., Hangzhou, China
fYear :
2015
Firstpage :
208
Lastpage :
213
Abstract :
In gird-connected power electronic systems, a fast and accurate tracking method of fundamental grid voltage is required to synchronize the converters with the mains. The Synchronous Reference Frame (SRF) based voltage magnitude and phase detection method is able to track three phase balanced grid voltage. But its performance is very poor when the gird-voltage is unbalanced and/or distorted. Improved SRF based detection methods can partially achieve either fast postfault resynchronization or steady-state unbalanced and distorted voltage rejection. However, its overall performance is not satisfying. This paper proposes a novel detection method based on SRF Phase-Locked Loop (PLL), in which a Low Pass Filter (LPF) and a Phase Sequence Separator (PSS) are combined to reach a tradeoff between fast detection speed and steady-state detection accuracy. Simulation including comparison of traditional methods and the proposed one under different grid fault conditions has been performed. The results validate the correctness and effectiveness of the proposed strategy.
Keywords :
low-pass filters; phase locked loops; power grids; power system faults; synchronisation; LPF; PLL loop filter; PSS; SRF based voltage magnitude; SRF phase-locked loop; distorted grid voltage; distorted voltage rejection; grid fault conditions; low pass filter; magnitude detection; phase detection method; phase sequence separator; phase synchronization; steady-state unbalanced voltage; synchronous reference frame; three phase balanced grid voltage; unbalanced grid voltage; Harmonic analysis; Phase distortion; Phase locked loops; Power harmonic filters; Steady-state; Synchronization; Voltage fluctuations; filter; phase locked loop; synchronous reference frame; unbalanced and distorted; voltage faults;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Power Electronics and Drive Systems (PEDS), 2015 IEEE 11th International Conference on
Conference_Location :
Sydney, NSW
Type :
conf
DOI :
10.1109/PEDS.2015.7203406
Filename :
7203406
Link To Document :
بازگشت