Title :
High efficient 3-input XOR for low-voltage low-power high-speed applications
Author :
Cheng, Kuo-Hsing ; Hsieh, Ven-Chieh
Author_Institution :
Dept. of Electr. Eng., Tamkang Univ., Tamsui, Taiwan
fDate :
6/21/1905 12:00:00 AM
Abstract :
A new 3-input XOR gate based upon the pass transistor design methodology for low-voltage, low-voltage high-speed applications is proposed. Five existing circuits are compared with the new proposed gate. It is shown that the proposed new circuit has at least 50% improvement in power-delay product than that of the CPL structure and the CMOS structure. Moreover, the proposed new circuit can also be operated as low as 1 V. Thus, the proposed new circuit is suitable for low-power, low-voltage and high-speed applications
Keywords :
CMOS logic circuits; delays; high-speed integrated circuits; logic design; logic gates; low-power electronics; ternary logic; 0.35 micron; 1 V; 3-input XOR gate; CMOS logic gate; exclusive OR gate; high-speed applications; low-power applications; low-voltage applications; pass transistor design methodology; power-delay product; Adders; CMOS technology; Circuit simulation; Combinational circuits; Design methodology; Logic circuits; MOS devices; Power measurement; Signal design; Voltage;
Conference_Titel :
ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on
Conference_Location :
Seoul
Print_ISBN :
0-7803-5705-1
DOI :
10.1109/APASIC.1999.824054
