A 1.5 V 10-bit 25 MSPS pipelined A/D converter

Author

Choi, Hee Cheol ; Park, Ho-Jin ; Hwang, Sung-Sik ; Bae, Shin-Kyu ; Kim, Jae-Whui ; Chung, Philip

Author_Institution

Syst. LSI Div., Samsung Electron. Co., Yongin, South Korea

fYear

1999

fDate

6/21/1905 12:00:00 AM

Firstpage

170

Lastpage

173

Abstract

A 1.5 V 10-bit 25 MSPS pipelined analog-to-digital converter was implemented using 0.25 μm CMOS technology. The converter is based on low-voltage two-stage opamps and a current reference generator for low-voltage operation. It also employs a novel dual-mode voltage booster to achieve good low-voltage operation as well as cost reduction. The current reference generator adopts a newly proposed self charge-pumping architecture with ring oscillator that keeps a reference current constant regardless of temperature and voltage variations under the low-voltage environment. The ADC occupies a die area of 2.21 mm² (1700 um×1300 um) and dissipates 45 mW at 25 MHz clock rate with 1.5 V single supply voltage in measurement result. Typical differential nonlinearity (DNL) and integral nonlinearity (INL) are ±0.44 LSB and ±0.82 LSB, respectively

Keywords

CMOS integrated circuits; analogue-digital conversion; low-power electronics; pipeline processing; 0.25 micron; 1.5 V; 10 bit; 25 MHz; 45 mW; CMOS technology; DNL; INL; LV two-stage opamps; analog-to-digital converter; current reference generator; differential nonlinearity; dual-mode voltage booster; integral nonlinearity; low-voltage opamps; low-voltage operation; pipelined A/D converter; pipelined ADC; ring oscillator; self charge-pumping architecture; Analog-digital conversion; Area measurement; CMOS technology; Charge pumps; Clocks; Costs; Ring oscillators; Temperature; Voltage; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-5705-1

Type

conf

DOI

10.1109/APASIC.1999.824055

Filename

824055