Title :
Design and implementation of a novel Boundary-Scan circuit in an SOI-Based FPGA
Author :
Wu, Lihua ; Chen, Stanley L. ; Han, Xiaowei ; Zhao, Yan ; Liu, Zhongli ; Li, Yan
Author_Institution :
Inst. of Semicond., Chinese Acad. of Sci., Beijing, China
Abstract :
A novel Boundary-Scan circuit compatible with IEEE 1149.1 standard and designed for our SOI-Based FPGA is presented in this paper. The new Boundary-Scan circuit serves the test of FPGA at the chip as well as board level and the added features facilitate the configuration and verification functions of FPGA. The Boundary-Scan circuit in this paper has been implemented in an SRAM-Based FPGA fabricated by a 0.5μm SOI-CMOS process. The test results from the fabricated chip demonstrate that this circuit successfully realizes the desired functions in programming, verification and testing.
Keywords :
CMOS digital integrated circuits; SRAM chips; boundary scan testing; field programmable gate arrays; integrated circuit design; integrated circuit testing; silicon-on-insulator; IEEE 1149.1 standard; SOI-CMOS process; SRAM-Based FPGA; boundary-scan circuit; Built-in self-test; Circuit synthesis; Decoding; Field programmable gate arrays; Programming; Registers; System-on-a-chip;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-5797-7
DOI :
10.1109/ICSICT.2010.5667793
