DocumentCode :
1641088
Title :
A low-power matrix transposer using MSB-controlled inversion coding
Author :
Kim, Kyeounsoo ; Beerel, Peter A.
Author_Institution :
Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
fYear :
1999
fDate :
6/21/1905 12:00:00 AM
Firstpage :
194
Lastpage :
197
Abstract :
This paper proposes a low-overhead MSB-controlled inversion coding technique to reduce the transition activity in a matrix transposer a commonly used component in 2-dimensional discrete cosine transform (DCT) and inverse DCT (IDCT) applications. A family of designs is identified in which this technique is applied to different bit slices of the matrix data and the optimal design within the family is determined using transition activity analysis driven by real image sequences. Our results suggest that the optimal design using MSB-controlled inversion coding yields power savings of 33% for DCT data and 46% for IDCT data. These results are remarkable since existing bus-invert coding techniques have high overheads and are only effective for system-level high-capacitive buses
Keywords :
application specific integrated circuits; digital signal processing chips; discrete cosine transforms; image coding; image sequences; low-power electronics; matrix algebra; parallel architectures; 2D DCT; ASIC; DSP chip; IDCT applications; MSB-controlled inversion coding; discrete cosine transform; inverse DCT; low-power matrix transposer; power savings; real image sequences; transition activity analysis; transition activity reduction; Array signal processing; Batteries; Capacitance; Discrete cosine transforms; Image analysis; Image sequence analysis; Image sequences; Multiplexing; Registers; Switching circuits;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on
Conference_Location :
Seoul
Print_ISBN :
0-7803-5705-1
Type :
conf
DOI :
10.1109/APASIC.1999.824061
Filename :
824061
Link To Document :
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