Title :
A 1.2V 1Mbit embedded MRAM core with folded bit-line array architecture
Author :
Tsuji, Takaharu ; Tanizaki, Hiroaki ; Ishikawa, Masatoshi ; Otani, Jun ; Yamaguchi, Yuichiro ; Ueno, Shuichi ; Oishi, Tsukasa ; Hidaka, Hideto
Author_Institution :
MCU&SOC Bus. Unit, Renesas Technol. Corp., Itami, Japan
Abstract :
A 1Mbit MRAM with a 0.81 μm2 1-Transistor 1-Magnetic Tunnel Junction (1Tr-1MTJ) cell using 0.13 μm 4LM logic technology has been produced. A folded-bitline sensing and common write word-line scheme with dummy row architecture achieves 100MHz random read cycle with n+ diffusion/Co-silicide read source lines. Employing a distributed gate voltage control scheme, high speed write current switching without write disturb by peak current even at 1.2V power supply is demonstrated.
Keywords :
magnetic film stores; magnetic tunnelling; random-access storage; 0.13 μm 4LM logic technology; 0.13 micron; 1 Mbit; 1.2 V; 1.2V 1Mbit embedded MRAM core; 100 MHz; 100MHz random read cycle; distributed gate voltage control scheme; dummy row architecture; folded bit-line array architecture; high speed write current switching; magnetic tunnel junction; CMOS logic circuits; CMOS technology; Large scale integration; Logic arrays; Logic devices; Magnetic switching; Magnetic tunneling; Manufacturing; Power capacitors; Switches;
Conference_Titel :
VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on
Print_ISBN :
0-7803-8287-0
DOI :
10.1109/VLSIC.2004.1346647
