DocumentCode
1641101
Title
A lossless index coding algorithm and VLSI design for vector quantization
Author
Sheu, Ming-hwa ; Tsai, Sh-Chi ; Shieh, Ming-Der
Author_Institution
Dept. of Electron. Eng., Nat. Yunlin Univ. of Sci. & Technol., Taiwan
fYear
1999
fDate
6/21/1905 12:00:00 AM
Firstpage
198
Lastpage
201
Abstract
This paper presents a switching-tree coding (STC) algorithm to re-encode the output codevector indexes after vector quantization. Based on the connections in the index neighborhood, we construct three binary trees to allocate the optimal variable-length noiseless code for each index. Simulation results indicate that this algorithm can improve coding efficiency without introducing any extra coding distortion, as compared to conventional memoryless VQ. Besides, according the new algorithm, an efficient VLSI architecture is also derived under the requirements of low cost and high performance. The gate counts of encoder and decoder are about 5000 and 4800 respectively. After Verilog simulation, the clock rate of the whole architecture is 50 MHz by using 0.6 μm CMOS IP3M technology
Keywords
CMOS digital integrated circuits; VLSI; application specific integrated circuits; decoding; digital signal processing chips; high-speed integrated circuits; image coding; vector quantisation; 0.6 micron; 50 MHz; ASIC; CMOS IP3M technology; DSP chip; VLSI design; VQ; binary trees; coding efficiency; decoder; efficient VLSI architecture; encoder; image compression; lossless index coding algorithm; optimal variable-length noiseless code; output codevector indexes; switching-tree coding algorithm; vector quantization; Algorithm design and analysis; Binary trees; Costs; Decoding; Encoding; Hardware design languages; Image coding; Pixel; Vector quantization; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on
Conference_Location
Seoul
Print_ISBN
0-7803-5705-1
Type
conf
DOI
10.1109/APASIC.1999.824062
Filename
824062
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