DocumentCode
1641139
Title
Low-power full-search motion estimator architecture suitable for random-block match
Author
Kim, Kyung-Saeng ; Lee, Dong-Jae ; Hoi-Jun Yoo ; Lee, Kwyro
Author_Institution
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea
fYear
1999
fDate
6/21/1905 12:00:00 AM
Firstpage
210
Lastpage
212
Abstract
We propose a new motion estimator with two types of embedded memory banks. Its overall system efficiency is extremely high for full-search block match algorithm (FBMA). The results show that its power-area product is nearly 1.13 and switching-overhead is low between FBMA and random-search block match algorithm in the case of CCIR-601 format
Keywords
VLSI; application specific integrated circuits; digital signal processing chips; image matching; low-power electronics; motion estimation; pipeline processing; search problems; CCIR-601 format; DSP chip; VLSI architecture; embedded memory banks; full-search block match algorithm; full-search motion estimator architecture; low-power motion estimator architecture; power-area product; random-block matching; system efficiency; Clocks; Code standards; Computer architecture; Image quality; Motion estimation; Pipelines; Read-write memory; Systolic arrays; Very large scale integration; Video codecs;
fLanguage
English
Publisher
ieee
Conference_Titel
ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on
Conference_Location
Seoul
Print_ISBN
0-7803-5705-1
Type
conf
DOI
10.1109/APASIC.1999.824065
Filename
824065
Link To Document