A dual issue queued pipelined Java processor TRAJA-toward an open source processor project

Author

Shimizu, Naohiko ; Naito, Makoto

Author_Institution

Sch. of Eng., Tokai Univ., Hiratsuka, Japan

fYear

1999

fDate

6/21/1905 12:00:00 AM

Firstpage

213

Lastpage

216

Abstract

In this paper the authors present a dual issue queued pipelined Java processor TRAJA 3.0. It can decode 162 instructions of the Java Virtual Machine (JVM)´s opcodes and it has a set of proprietary instructions. The pipeline has four instruction buffers and four decode queues to overcome the pipeline stalls on decoding the variable length instructions of the JVM. The processor also executes a restricted set of instruction folding and a restricted set of instruction reorder. In addition it has a caching scheme for the fast execution of the array instructions of the JVM

Keywords

Java; instruction sets; microprocessor chips; parallel architectures; pipeline processing; Java Virtual Machine opcodes; TRAJA 3.0; array instructions; array reference cache; caching scheme; dual issue queued pipelined Java processor; instruction buffers; instruction folding; instruction reorder; open source processor project; proprietary instructions; variable length instructions; Application software; Counting circuits; Decoding; Java; Licenses; Microprogramming; Operating systems; Pipelines; Runtime; Virtual machining;

fLanguage

English

Publisher

ieee

Conference_Titel

ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-5705-1

Type

conf

DOI

10.1109/APASIC.1999.824066

Filename

824066