Title :
RAPTOR: a single chip multiprocessor
Author :
Lee, Sang-Won ; Song, Yun-Seob ; Kim, Soo-Won ; Oh, Hyeong-Cheol ; Hahn, Woo-Jong
Author_Institution :
Dept. of Electron. Eng., Korea Univ., Seoul, South Korea
fDate :
6/21/1905 12:00:00 AM
Abstract :
A microarchitecture of a processor named RAPTOR is described. RAPTOR is a single chip multiprocessor developed for exploiting thread-level parallelism. RAPTOR includes four identical processors, a graphics coprocessor, and an external cache controller. Each processor has a 16 KB primary cache and implements SPARC version 9 instruction set architecture. The external cache controller provides direct connection to a large external second level cache. RAPTOR is designed as a building block of multiprocessor systems such as symmetric multiprocessor machines
Keywords :
VLSI; microprocessor chips; multiprocessing systems; parallel architectures; pipeline processing; reduced instruction set computing; 16 KB; RAPTOR; RISC processors; SPARC version 9 instruction set architecture; external cache controller; external second level cache; graphics coprocessor; microarchitecture; single chip multiprocessor; thread-level parallelism; Circuits; Concurrent computing; Coprocessors; Graphics; Hardware; Microarchitecture; Multiprocessing systems; Operating systems; Parallel processing; Yarn;
Conference_Titel :
ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on
Conference_Location :
Seoul
Print_ISBN :
0-7803-5705-1
DOI :
10.1109/APASIC.1999.824067
