DocumentCode :
164134
Title :
Reliability enhanced SRAM bit-cells
Author :
Beiu, V. ; Tache, M. ; Kharbash, F.
Author_Institution :
Coll. of Inf. Technol., United Arab Emirates Univ., Al Ain, United Arab Emirates
fYear :
2014
fDate :
13-15 Oct. 2014
Firstpage :
229
Lastpage :
232
Abstract :
Noises and variations are ubiquitous, but are ill-understood and in most cases analyzed simplistically, leading to substantial overdesign costs. A novel reliability-centric design method based on unconventionally sizing transistors has been suggested lately. In this paper our aim is to design, simulate, and compare the benefits of unconventional sizing when applied to SRAM bit-cells. The unconventionally sized SRAM bit-cells achieve higher SNMs, having the potential to work correctly at supply voltages lower than those achieved using classically sized SRAM bit-cells.
Keywords :
SRAM chips; integrated circuit reliability; SNM; reliability enhanced SRAM bit-cell; reliability-centric design method; static noise margin; static random-access memory; unconventional sizing transistor; Logic gates; Noise; Optimized production technology; Reliability; SRAM cells; Transistors; CMOS; SNM; SRAM; reliability; sizing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Semiconductor Conference (CAS), 2014 International
Conference_Location :
Sinaia
ISSN :
1545-827X
Print_ISBN :
978-1-4799-3916-9
Type :
conf
DOI :
10.1109/SMICND.2014.6966444
Filename :
6966444
Link To Document :
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