Design technique for interpolated flash ADC

Analog-to-digital conversion plays an essential role in all kinds of electronics systems, including signal processing, communications and storage. In particular, interpolated flash ADC has been widely used in high-speed systems requiring very high sampling speed. Obviously, practical ADC design is very challenging, which has been dominated by experiences and trial-and-error skills. This is true to flash ADC designs too where circuit designers have often been puzzled by complex factors between ADC chip performance and its architecture, circuit, device and technological details. As system performance continues advance and market demands intensify rapidly, it is imperative for designers to make quick and rational decisions in ADC designs to balance various design factors. This paper reports a comprehensive design matrix analysis and quantitative design approach for capacitive interpolated flash ADCs aiming to address the design challenges. It describes quantitatively the complex relationship among critical factors including ADC speed, interpolation, stage number, pre-amplifier bandwidth, transistor parasitic effects, transistor size and technology parameters, etc. The quantitative design technique intends to enable designers to make rapid and predictive decisions in flash ADC designs to achieve both trade-offs and performance optimization in practice. Design examples in 90/130nm CMOS are presented.