A VLSI design of hierarchical search motion estimation processor chip

Author

Seo, Young San ; You, Jae Hee

Author_Institution

Sch. of Electr. Eng., Hongik Univ., Seoul, South Korea

fYear

1999

fDate

6/21/1905 12:00:00 AM

Firstpage

247

Lastpage

249

Abstract

This paper presents a motion estimation processor that has regular and simple structure and achieves 100% hardware utilization without image data fill time. It can compute half-pel precision estimation and I/O bottleneck is eliminated using a small distributed on-chip image memory. The number of processing elements is scalable according to the degree of parallel processing and throughput requirements. It has been designed and verified with C++ and VHDL

Keywords

CMOS digital integrated circuits; VLSI; application specific integrated circuits; digital signal processing chips; formal verification; integrated circuit design; motion estimation; parallel architectures; CMOS DSP chip; VHDL; VLSI design; distributed onchip image memory; half-pel precision estimation; hierarchical search; motion estimation processor chip; parallel processing; Application specific integrated circuits; Computer architecture; Data compression; Distributed computing; Hardware; Motion estimation; Parallel processing; Throughput; Transform coding; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-5705-1

Type

conf

DOI

10.1109/APASIC.1999.824075

Filename

824075