DocumentCode
1641421
Title
ESD design for power analog circuit
Author
Vashchenko, V.A. ; Shibkov, A.A.
Author_Institution
Nat. Semicond. Corp., Santa Clara, CA, USA
fYear
2010
Firstpage
172
Lastpage
175
Abstract
A non-trivial nature of the power management circuit design is emphasized based on three case studies. The events of transient latchup and device failure under Charged Device Model (CDM) pulse due to an unexpected current path in power analog circuits are analyzed demonstrating the value of mixed-mode simulation approach.
Keywords
analogue integrated circuits; electrostatic discharge; integrated circuit design; mixed analogue-digital integrated circuits; ESD design; charged device model pulse; device failure; mixed-mode simulation approach; power analog circuit; power management circuit design; transient latchup; Arrays; Clamps; Electrostatic discharge; Logic gates; Pins; Transient analysis; Voltage measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location
Shanghai
Print_ISBN
978-1-4244-5797-7
Type
conf
DOI
10.1109/ICSICT.2010.5667808
Filename
5667808
Link To Document