Implementation of 13 kbps QCELP vocoder ASIC

In this paper an efficient implementation of a 13 kbps QCELP vocoder ASIC having a speech compression function used in the digital mobile communication is presented The 13 kbps QCELP algorithm has better quality than 8 kbps one, but it requires much more computation. Especially, the complexity load of the pitch and codebook search process for speech synthesis is predominant. We propose an optimized routine for convolution computation by utilizing pipeline structure characteristics of the DSP. Our DSP, specifically designed for vocoder applications, is a 16-bit fixed-point one. We adopt RISC type instruction set, distributed decoding, alternative program fetch, dual bank memory structure, and repeat loop without loss in order to reduce the power consumption and to obtain fast operating capability while keeping the chip size small. The concurrent development of the DSP and the QCELP assembly code enables us to optimize the assembly code more successfully than adopting other general-purpose DSP chips