Title :
Design of a high performance microcontroller
Author :
Yue-li, Hu ; Jia-lin, Cao ; Feng, Ran ; Zhi-jian, Liang
Author_Institution :
Sch. of Mechatronical Eng. & Autom., Shanghai Univ., China
Abstract :
A high performance 8-bit microcontroller, which shares the same instruction set with the standard Intel 8051, is presented in this paper. In system architecture, four-clock period per machine cycle architecture, Harvard architecture and pre-fetching instruction method are adopted to improve MCU´s power efficiency. In CPU architecture, ALU of purely combinational circuits, Independent multiplier and divider module, multi-clocks architectures and hardwired control unit are adopted to get high speed. Considering power consumption, gating clock method is used to reduce the power consumption. Mapped in CSMC06 0.6μm CMOS technology, this MCU is successfully synthesized and simulated with EDA tools and implemented in FPGA of Altera´s APEX20KE. As an IP core, the MCU core can be conveniently involved in SOC.
Keywords :
CMOS integrated circuits; combinational circuits; electronic design automation; instruction sets; logic gates; microcontrollers; 0.6 micron; 8 bit; ALU; Altera APEX20KE; CMOS technology; CPU architecture; EDA tools; FPGA; Harvard architecture; IP core; Intel 8051; MCU core; MCU power efficiency; SOC; clock period per machine cycle; combinational circuits; divider module; gating clock method; hardwired control unit; high performance microcontroller; instruction set; multiclocks architectures; multiplier module; power consumption reduction; pre-fetching instruction method; system architecture; CMOS technology; Central Processing Unit; Circuit simulation; Circuit synthesis; Clocks; Combinational circuits; Electronic design automation and methodology; Energy consumption; Field programmable gate arrays; Microcontrollers;
Conference_Titel :
High Density Microsystem Design and Packaging and Component Failure Analysis, 2004. HDP '04. Proceeding of the Sixth IEEE CPMT Conference on
Print_ISBN :
0-7803-8620-5
DOI :
10.1109/HPD.2004.1346667