A 3.3 V high speed CMOS PLL with a two-stage self-feedback ring oscillator

Author

Moon, Yeon Kug ; Yoon, Kwang Sub

Author_Institution

Dept. of Electron. Eng., Inha Univ., Inchon, South Korea

fYear

1999

fDate

6/21/1905 12:00:00 AM

Firstpage

287

Lastpage

290

Abstract

A 3.3 V PLL (Phase Locked loop) is designed for high frequency, low voltage, and low power applications. This paper proposes a new PLL architecture to improve voltage-to-frequency linearity of the VCO (Voltage Controlled Oscillator) with new delay cell. The proposed VCO operates at a wide frequency range of 30 MHz~1 GHz with a good linearity. The DC-DC voltage up/down converter is newly designed to regulate the control voltage of the two-stage VCO. The designed PLL architecture is implemented on a 0.6 μm n-well CMOS process. The simulation results show a locking time of 2.6 μs at 1 GHz, lock in range of 100 MHz~1 GHz, and a power dissipation of 112 mW

Keywords

CMOS integrated circuits; UHF integrated circuits; feedback oscillators; high-speed integrated circuits; integrated circuit design; low-power electronics; mixed analogue-digital integrated circuits; phase locked loops; voltage-controlled oscillators; 0.6 micron; 112 mW; 2.6 mus; 3.3 V; 30 MHz to 1 GHz; DC-DC voltage up/down converter; PLL architecture; control voltage regulation; delay cell; high frequency applications; high speed CMOS PLL; low power applications; low voltage applications; n-well CMOS process; phase Locked loop; self-feedback ring oscillator; two-stage VCO; two-stage ring oscillator; voltage controlled oscillator; voltage-to-frequency linearity; CMOS process; DC-DC power converters; Delay; Frequency; Linearity; Low voltage; Phase locked loops; Power dissipation; Voltage control; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-5705-1

Type

conf

DOI

10.1109/APASIC.1999.824085

Filename

824085