A 0.7-1 Gb/s CMOS clock recovery circuit

Author

Wang, Hui ; Nottenburg, Richard

Author_Institution

Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA

fYear

1999

fDate

6/21/1905 12:00:00 AM

Firstpage

291

Lastpage

294

Abstract

A 0.7-1 Gb/s clock recovery circuit is designed by ruing a 0.5 μm digital CMOS process. It consists of a bang-bang type frequency detector (FD) to acquire frequency lock and a linear phase detector (PD) to acquire phase lock. The FD is able to reset itself upon frequency lock. Measured RMS jitter of the recovered clock is 7.4 ps at 1 GHz and 7 ps at 0.7 GHz. It is able to maintain a BER better than 10^-11 for up to 140 missing transitions. It consumes 200 mW with a 5 V power supply

Keywords

CMOS digital integrated circuits; application specific integrated circuits; digital phase locked loops; error statistics; high-speed integrated circuits; synchronisation; timing circuits; 0.5 micron; 0.7 to 1 Gbit/s; 200 mW; 5 V; BER; CMOS clock recovery circuit; bang-bang type; bit error rate; digital CMOS process; frequency detector; frequency lock; linear phase detector; loop analysis; Bandwidth; Circuit optimization; Clocks; Jitter; Optical signal processing; Phase frequency detector; Power supplies; Quantum cascade lasers; Tuning; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-5705-1

Type

conf

DOI

10.1109/APASIC.1999.824086

Filename

824086