Title :
Design with testability for a platform-based SoC design methodology
Author :
Ke, Wuudiann ; Truong, Khoan
Author_Institution :
Cadence Design Syst. Inc., San Jose, CA, USA
fDate :
6/21/1905 12:00:00 AM
Abstract :
This paper describes a design-for-testability (DFT) methodology for an application-oriented platform-based design environment, which reuses test-ready virtual components (VCs) and integrates them using a set of predefined guidelines and practices. We focus on introducing the concept of the proposed methodology with examples for demonstrating some of the techniques and issues
Keywords :
application specific integrated circuits; circuit CAD; design for testability; integrated circuit design; integrated circuit testing; microprocessor chips; ASIC; DFT methodology; application-oriented platform-based design environment; design-for-testability methodology; platform-based SOC design methodology; system-on-a-chip design; virtual components reuse; Costs; Design for testability; Design methodology; Guidelines; Logic testing; Manufacturing; Production; System testing; Time to market; Virtual colonoscopy;
Conference_Titel :
ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on
Conference_Location :
Seoul
Print_ISBN :
0-7803-5705-1
DOI :
10.1109/APASIC.1999.824090
