Title :
A robust design of SRAM sense amplifier for submicron technology
Author :
Wang, Ziou ; Zhang, Yiping ; Zhang, Lijun ; Song, Xiaoyu
Author_Institution :
Sch. of Electron. & Inf. Eng., Soochow Univ., Suzhou, China
Abstract :
SRAM sense amplifier plays a key role in memory design. With technology scaling to the nanometer, the device mismatch increases and the distribution effect induces unstable signal injection, thus affecting the reliability of memory system. This paper presents a new method for SRAM sense amplifier design. It incorporates reasonable delay between the passgate and enable signals to effectively mitigates the failure ratio and keep the ratio less sensitive to signal slope. The novel amplifier structure is both simple and easy to control. A reliable design is given by considering both intrinsic and extrinsic offsets with reasonable speed and power consumption. A failure ratio analysis is performed. The result is validated using UMC 65nm process model.
Keywords :
SRAM chips; amplifiers; fault diagnosis; network synthesis; SRAM sense amplifier; UMC; distribution effect; failure ratio analysis; memory system; signal injection; submicron technology; Couplings; Delay; Latches; MOS devices; Power demand; Random access memory; Reliability engineering; SRAM; memory; offset; sense amplifier; slope;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-5797-7
DOI :
10.1109/ICSICT.2010.5667824
