Exceeding test pattern limitation by multi-clock test methodology

Author

Hwan, Jang Jin ; Ho, Kim Kyung ; Suk, Kye Bum

Author_Institution

Semicond. Syst. LSI Bus., Samsung Electron., Kyungki, South korea

fYear

1999

fDate

6/21/1905 12:00:00 AM

Firstpage

311

Lastpage

314

Abstract

There are some limitations in the ASIC test. The maximum test pattern depth is one of them. A method to reduce the test pattern depth would be very useful. Hence the authors introduce a method to do this and the target ATE is ADVAN

Keywords

application specific integrated circuits; automatic testing; integrated circuit testing; ADVAN ATE; ASIC test; maximum test pattern depth; multi-clock test methodology; test pattern limitation; Application specific integrated circuits; Benchmark testing; Clocks; Costs; Debugging; Large scale integration; Mass production; Performance evaluation;

fLanguage

English

Publisher

ieee

Conference_Titel

ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-5705-1

Type

conf

DOI

10.1109/APASIC.1999.824091

Filename

824091

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1641887