DocumentCode
1641907
Title
Input grouping method considering nodal connectivity for BIST test time reduction
Author
Choi, Byung-Gu ; Chang, Yoon-Seok ; Kim, Dong-wook
Author_Institution
Dept. of Electron. Mater. Eng., Kwangwoon Univ., Seoul, South Korea
fYear
1999
fDate
6/21/1905 12:00:00 AM
Firstpage
315
Lastpage
318
Abstract
At present, BIST is a major test strategy with features of automatic test and possibility of at-speed test. But BIST has significant problems for hardware overhead and consumes impractical test time (test length); in the case of CUT it has a large number of primary inputs. We proposed a new method called input grouping which is helpful to reduce test length for BIST application. This method partitions inputs by considering nodal connectivity with respect to internal nodes. To achieve this purpose we proposed some definitions for test points, conditions for a node to be a test point, and a procedure to find test points in a given circuits. The test points were applied to form a BIST structure to reduce the test time. The experimental result showed that BIST TPGs based on this method achieves tremendous reduction in test time compared to the case using pseudorandom patterns for various example circuits
Keywords
application specific integrated circuits; automatic test pattern generation; built-in self test; design for testability; integrated circuit testing; shift registers; BIST structure; BIST test time reduction; TPGs; at-speed test; automatic test; hardware overhead; input grouping method; nodal connectivity; pseudorandom patterns; test length; test time; Automatic testing; Built-in self-test; Circuit testing; Delay effects; Design for testability; Electronic equipment testing; Hardware; Materials testing; Performance evaluation; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on
Conference_Location
Seoul
Print_ISBN
0-7803-5705-1
Type
conf
DOI
10.1109/APASIC.1999.824092
Filename
824092
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