DocumentCode
1641994
Title
Wide operating-range acquisition technique for PLL circuits
Author
Chang, Yi-Cheng ; Greeneich, Edwin W.
Author_Institution
Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ, USA
fYear
1999
fDate
6/21/1905 12:00:00 AM
Firstpage
341
Lastpage
344
Abstract
A wide range phase-locked loop (PLL) circuit using a coarse-steering technique is designed for implementation in MOSIS 1.2 μm CMOS technology. The entire PLL circuit has been simulated and can obtain lock in over a frequency range of 160-440 MHz with a 3 volt power supply on HSPICE
Keywords
CMOS analogue integrated circuits; SPICE; phase locked loops; 1.2 micron; 160 to 440 MHz; 3 V; HSPICE simulation; MOSIS CMOS technology; coarse-steering; lock-in; phase-locked loop circuit; wide operating-range acquisition technique; Additives; CMOS technology; Counting circuits; Equations; Flip-flops; Frequency; Mirrors; Phase locked loops; Voltage control; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on
Conference_Location
Seoul
Print_ISBN
0-7803-5705-1
Type
conf
DOI
10.1109/APASIC.1999.824098
Filename
824098
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