Title :
A delay locked loop circuit with mixed-mode tuning
Author :
Song, Yeo-San ; Kang, Jin-Ku
Author_Institution :
Dept. of Electr. & Comput. Eng., Inha Univ., Inchon, South Korea
fDate :
6/21/1905 12:00:00 AM
Abstract :
This paper shows a DLL (delay locked loop) which has a mixed-mode tuning capability. The proposed architecture is based on a dual loop which is controlled by peripheral circuits such as FSM (finite state machine) and two phase detectors whose roles are coarse error detection and fine error detection respectively. The main DLL is composed of eight differential delay buffers and generates eight clocks evenly spaced by 45°. The second loop is to produce the retimed clock through coarse timing and fine timing using digital and analog phase control. The circuit has the unlimited phase control range due to the dial loop structure. The circuit operates at 500 MHz under 3.3 V supply according to SPICE simulation on the extracted layout. The circuit will be fabricated in 0.6-μm CMOS
Keywords :
CMOS analogue integrated circuits; SPICE; circuit simulation; circuit tuning; delay lock loops; error detection; finite state machines; phase detectors; 0.6 micron; 3.3 V; 500 MHz; FSM; SPICE simulation; coarse error detection; delay locked loop circuit; dial loop structure; differential delay buffers; fine error detection; finite state machine; mixed-mode tuning; peripheral circuits; phase detectors; retimed clock; unlimited phase control range; Automata; Circuit optimization; Clocks; Delay; Detectors; Error correction; Phase control; Phase detection; SPICE; Timing;
Conference_Titel :
ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on
Conference_Location :
Seoul
Print_ISBN :
0-7803-5705-1
DOI :
10.1109/APASIC.1999.824100
