Title :
Logic cell design for on-line testable FPGAs
Author :
Lala, P.K. ; Singh, A.
Author_Institution :
Dept. of Electr. Eng., Univ. of South Florida, Tampa, FL, USA
fDate :
6/21/1905 12:00:00 AM
Abstract :
This paper proposes a self-checking logic cell that can be used as the building block for on-line testable FPGAs. The proposed cell consists of three 4-to-1 multiplexers, a 2-to-1 multiplexers and a D flip-flop. These multiplexers and the D flip-flop are designed using differential cascode voltage switch logic. Any single transistor fault (stuck-on/off) as well as single stuck-at faults at the inputs of the multiplexers or the D flip-flop can be detected on-line
Keywords :
CMOS logic circuits; built-in self test; cellular arrays; fault diagnosis; field programmable gate arrays; flip-flops; logic testing; multiplexing equipment; D flip-flop; differential cascode voltage switch logic; logic cell design; multiplexers; on-line testable FPGAs; self-checking logic cell; single stuck-at faults; single transistor fault; Circuit faults; Circuit testing; Fault detection; Field programmable gate arrays; Flip-flops; Logic design; Logic functions; Logic testing; Multiplexing; Switches;
Conference_Titel :
ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on
Conference_Location :
Seoul
Print_ISBN :
0-7803-5705-1
DOI :
10.1109/APASIC.1999.824101
