Title :
On using ATPG vectors for BIST TPG
Author :
Asakawa, T. ; Iwasaki, K.
Author_Institution :
Graduate Sch. of Eng., Tokyo Metropolitan Univ., Japan
fDate :
6/21/1905 12:00:00 AM
Abstract :
We propose a method for designing a test pattern generator (TPG) to achieve high-fault coverage for stuck-at faults with short application time during BIST. The TPG consists of shift registers and a small amount of ROM containing test vectors generated by an ATPG tool. Experimental results show that our method can drastically reduce the test length required to achieve high-fault coverage with a small amount of hardware overhead in comparison with an LFSR-based method
Keywords :
automatic test pattern generation; built-in self test; fault diagnosis; ATPG vector; BIST TPG; ROM; fault coverage; shift register; stuck-at fault; test pattern generator; Automatic test pattern generation; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Clocks; Fault detection; Read only memory; Strontium; Test pattern generators;
Conference_Titel :
ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on
Conference_Location :
Seoul
Print_ISBN :
0-7803-5705-1
DOI :
10.1109/APASIC.1999.824104
