DocumentCode
1642124
Title
Test ready core design for TeakLite core
Author
Park, Heemin ; Sim, Gyoochan ; Jung, Jaehoon ; Jun, Hong-Shin
Author_Institution
ASIC Div., Samsung Electron. Co. Ltd., Kyunki, South Korea
fYear
1999
fDate
6/21/1905 12:00:00 AM
Firstpage
363
Lastpage
366
Abstract
This paper describes test ready core design methodology for TeakLite core. Implementation issues and techniques about test access with minimal test pins, scan chain reconfiguration, and UDL test capability are presented. Testability enhancement for development of high quality test vector is also described. As the result, a very high fault coverage of 99.68% has been achieved. We also present the features of test ready TeakLite core
Keywords
application specific integrated circuits; design for testability; digital signal processing chips; integrated circuit design; integrated circuit testing; ASIC; DSP; TeakLite core; fault coverage; scan chain reconfiguration; system-on-a-chip; test ready core design; test vector generation; user defined logic; Application specific integrated circuits; Circuit testing; Clocks; Consumer electronics; Degradation; Digital signal processing; Large scale integration; Logic testing; Pins; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on
Conference_Location
Seoul
Print_ISBN
0-7803-5705-1
Type
conf
DOI
10.1109/APASIC.1999.824107
Filename
824107
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