• DocumentCode
    1642131
  • Title

    A new method to reduce VDMOS on-resistance in BCD process

  • Author

    Zhang, Zhengyuan ; Feng, Zhicheng ; Mei, Yong ; Li, Jiangen ; Li, Xiaogang

  • Author_Institution
    Nat. Lab. of Analog Integrated Circuits, Chongqing, China
  • fYear
    2010
  • Firstpage
    117
  • Lastpage
    119
  • Abstract
    This paper focused on special requirement of low on-resistance of VDMOS in BCD process. VDMOS structure and its process were studied, and a method for decreasing on-resistance of VDMOS was developed. In this method, a 10 μm deep trapezia ring was formed on the N+ ring of D electrode of VDMOS, and a few more steps were added to ordinary BCD process. Using the method, N-type VDMOS transistor with low on-resistance was obtained, which is approximately 30% lower than that of similar device in BCD process. For the new N-type VDMOS, BVDS and VT is 80 V and 2.5 V, respectively.
  • Keywords
    MOS integrated circuits; BCD process; on-resistance; reduce VDMOS; trapezia ring; voltage 2.5 V; voltage 80 V; Annealing; Doping; Electrodes; Integrated circuits; Resistance; Substrates; Transistors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
  • Conference_Location
    Shanghai
  • Print_ISBN
    978-1-4244-5797-7
  • Type

    conf

  • DOI
    10.1109/ICSICT.2010.5667833
  • Filename
    5667833
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1642131