A multi parametric optimization based novel approach for an efficient design space exploration for ASIC design

High level synthesis (HLS) is the methodology of generating Register Transfer Logic(RTL) design taking into consideration the behavioural specification and constraints within an optimized cost function. Design space exploration (DSE), an important stage of HLS, is a task for identifying and evaluating design alternatives during system development for obtaining Pareto optimal solution. Concerns over the power dissipation coupled with the conventional metrics such as area, time delay, thermal, performance, reliability, cost and testability have raised the demand for an efficient technique of high level synthesis with better design space exploration. This paper presents a novel approach to achieve a Pareto optimal solution for this design space exploration in minimum possible design time using Greedy Algorithm and Priority Factor (PF) for power and timing analysis.