Analyze and reduce the impact of sampling delay on LCL converter with capacitor current feedback active damping

The capacitor current feedback active damping is widely used in LCL converter. However, digital processor needs some time to calculate the output in digital control system which will result in sampling delay. The sampling delay will leads to system instability and unacceptable damping performance, especially in low switching frequency. This paper overcomes this issue by shifting the sampling instant close to the PWM updating instant. This approach can strengthen system stability and achieve sufficient active damping. Moreover, smaller sampling delay corresponds to larger damping ratio. The theoretical conclusions presented in this paper are verified by simulation and experiment.