DocumentCode :
1642365
Title :
Automated test bitstream generation for an SOI-based FPGA
Author :
Li, Yan ; Chen, Stanley L. ; Chen, Liang ; Zhang, Qianli ; Li, Ming
Author_Institution :
Inst. of Semicond., Chinese Acad. of Sci., Beijing, China
fYear :
2010
Firstpage :
1976
Lastpage :
1978
Abstract :
In this paper, we propose a methodology of the automated bitstream generation for conducting high-testability FPGA tests. In order to study the efficiency of our solution we will explore our methodology in the test of an SOI-based FPGA. We use a semi-automated approach of the bitstream generation for ease of test vector design with high functionality and fault coverage. The methodology from this research is extensively exercised in the design process. The quality of this methodology is proven by the efficiency of the test vector suite used in the wafer and packaged tests. The same approach can also be used in the bitstream generation for FPGA application.
Keywords :
field programmable gate arrays; logic testing; silicon-on-insulator; SOI-based FPGA; automated test bitstream generation; test vector design; Arrays; Field programmable gate arrays; Hardware design languages; Silicon; Solid modeling; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-5797-7
Type :
conf
DOI :
10.1109/ICSICT.2010.5667840
Filename :
5667840
Link To Document :
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