• DocumentCode
    1642367
  • Title

    Fast simulation of turbo codes on GPUs

  • Author

    Chinnici, Stefano ; Spallaccini, Paolo

  • Author_Institution
    PDU Microwave & Mobile Backhaul, Ericsson Telecomun. SpA, Milan, Italy
  • fYear
    2012
  • Firstpage
    61
  • Lastpage
    65
  • Abstract
    Simulation of turbo codes with moderately long block lengths down to bit error rates of the order of 10-9 requires long runtimes on conventional CPUs. The approach described in this paper is based on a CPU/GPU co-processing strategy which aims at effectively distributing the processing tasks between the two platforms. In this paper, the most computationally intensive parts of turbo codes simulation are analyzed and their implementation on the GPU parallel architecture is discussed. Results on a case study for a serial concatenated convolutional code are presented, showing a simulation speed-up in excess of 10×. These initial results show that the CPU/GPU approach is a powerful tool that allows the characterization of the high SNR behavior of turbo codes with a short simulation runtime.
  • Keywords
    graphics processing units; parallel architectures; turbo codes; CPU-GPU coprocessing strategy; GPU parallel architecture; bit error rates; conventional CPU; turbo codes simulation; Bit error rate; Computational modeling; Decoding; Graphics processing unit; Iterative decoding; Quadrature amplitude modulation; Turbo codes; GPU; SCCC; turbo codes;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Turbo Codes and Iterative Information Processing (ISTC), 2012 7th International Symposium on
  • Conference_Location
    Gothenburg
  • ISSN
    2165-4700
  • Print_ISBN
    978-1-4577-2114-4
  • Electronic_ISBN
    2165-4700
  • Type

    conf

  • DOI
    10.1109/ISTC.2012.6325199
  • Filename
    6325199