Title :
A 3-cycle lock time delay-locked loop with a parallel phase detector for low power mobile systems
Author :
Miyazaki, Masayuki ; Ishibashi, Koichiro
Author_Institution :
Central Res. Lab., Hitachi Ltd., Kokubunji, Japan
fDate :
6/21/1905 12:00:00 AM
Abstract :
We have developed a delay-locked loop (DLL) which has a parallel phase-detector for generating a system clock in LSIs. The generated clock is synchronized to an internal clock for various loads in a system. The DLL achieves a settling time of 3 clock-cycles and a maximum skew of 150 ps. The operating frequency is from 66 MHz to 230 MHz with a typical power consumption of 13.5 mW at 100 MHz. In addition, due to the short settling time, the DLL can be powered down to reduce the standby current
Keywords :
CMOS digital integrated circuits; clocks; delay lock loops; low-power electronics; phase detectors; synchronisation; 0.25 mum; 13.5 mW; 3-cycle lock time delay-locked loop; 66 to 230 MHz; CMOS process; DLL; LSIs; clock synchronization; low power mobile systems; maximum skew; operating frequency; parallel phase detector; power consumption; settling time; standby current reduction; system clock generation; Circuits; Clocks; Control systems; Delay effects; Delay lines; Detectors; Frequency synchronization; Phase detection; Phase locked loops; Power generation;
Conference_Titel :
ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on
Conference_Location :
Seoul
Print_ISBN :
0-7803-5705-1
DOI :
10.1109/APASIC.1999.824117
